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Interconnection Structures in Multiprocessor Systems

In a multiprocessor system, the physical arrangement of communication paths between processors, memory modules, and I/O devices is known as the interconnection structure. The choice of structure affects the system's cost, complexity, and throughput.

1. Time-Shared Common Bus

This is the simplest interconnection structure. All processors, memory units, and I/O devices are connected to a single common bus. Only one unit can use the bus at a time.

  • **Advantage:** Low cost and simple hardware.
  • **Disadvantage:** Serious bottleneck; as more processors are added, performance drops due to bus contention.

2. Multiport Memory

In this structure, each memory module has multiple independent ports. This allows different processors to access the same or different memory modules simultaneously without using a shared bus.

  • **Advantage:** High throughput and parallel access.
  • **Disadvantage:** High hardware cost due to complex memory control logic and massive wiring.

3. Crossbar Switch

A crossbar switch consists of a grid of switches at every intersection of processor and memory lines. Any processor can be connected to any memory module by closing the switch at the corresponding junction.

  • **Advantage:** Supports the highest number of simultaneous transfers.
  • **Disadvantage:** Complexity increases exponentially ($n imes m$) with the number of units.

4. Multistage Switching Network

This is a compromise between the simple bus and the complex crossbar. It uses multiple stages of small switches (like 2x2 switches) to route paths between processors and memory.

Comparison Table

StructureComplexityCostThroughput
Common BusLowestLowestLow
Multiport MemoryHighHighHigh
Crossbar SwitchHighestHighestHighest
Multistage NetworkMediumMediumMedium

Common Mistakes to Avoid

  • Assuming a 'Common Bus' can support parallel memory access (it is strictly sequential).
  • Confusing 'Multiport Memory' with 'Dual-Channel RAM' (multiport allows independent CPU paths).
  • Underestimating the cabling mess created by a fully connected crossbar switch.
  • Thinking a multistage network is faster than a crossbar (it has higher latency due to stages).

Advanced Concepts

  • Hypercube Interconnection
  • Mesh and Torus Topologies
  • Omega and Butterfly Networks
  • Non-blocking vs. Blocking Networks
  • Network-on-Chip (NoC)

Practice Exercises

  • Calculate the number of switches required for a 16x16 crossbar switch.
  • Explain why a common bus is unsuitable for a 100-processor system.
  • Compare the reliability of a multiport memory system vs. a crossbar switch.
  • Research why modern supercomputers use Torus or Fat-tree topologies.

Conclusion

Interconnection structures define the scaling limits of a computer system. While simple buses suffice for PCs, high-performance computing requires advanced crossbar or multistage networks to ensure that processors are never starved of data.

Note: Note: Modern multi-core CPUs often use 'Ring Bus' or 'Mesh' interconnections to connect internal cores and caches efficiently.