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Priority Interrupt Handling

In a complex computer system, multiple I/O devices may request service at the same time. A priority interrupt system establishes an order of importance to determine which device is served first. This can be implemented using hardware (Daisy Chaining) or software (Polling).

1. Daisy Chaining (Serial Priority)

In a daisy chain, all devices are connected in series. The device physically closest to the CPU has the highest priority. If a device requests an interrupt, it blocks the 'Interrupt Acknowledge' signal from reaching devices further down the line.

  • **Advantage:** Simple hardware and easy to add new devices.
  • **Disadvantage:** Slow propagation of the acknowledge signal; if one device fails, the chain is broken.

2. Parallel Priority Interrupt

This method uses a specialized hardware circuit called a Priority Encoder. Each device has its own interrupt request line connected to the encoder. The encoder outputs the binary address of the highest-priority device currently requesting service.

  • **Interrupt Register:** Stores the pending interrupt requests from various devices.
  • **Mask Register:** Allows the CPU to selectively ignore (mask) specific interrupts.
  • **Priority Encoder:** Selects the highest priority request and generates the vector address for the CPU.

Comparison Table

FeatureDaisy Chaining (Serial)Parallel Priority
SpeedSlow (Propagation delay)Very Fast
Hardware CostLowHigh (Needs Encoder/Registers)
ScalabilityEasy to add devicesDifficult (Fixed encoder inputs)
ReliabilitySingle point of failureMore robust

Interrupt Masking

The CPU uses a Mask Register to control which interrupts can trigger the processor. By setting or clearing bits in this register, the programmer can disable lower-priority interrupts while a critical high-priority task is being executed.

Common Mistakes to Avoid

  • Confusing 'Bus Arbitration' with 'Interrupt Priority' (one is for bus access, the other for CPU attention).
  • Assuming Daisy Chaining is the fastest (it's actually the slowest due to serial propagation).
  • Forgetting that a Mask Register only disables 'Maskable' interrupts; 'Non-Maskable' interrupts (NMI) are always processed.
  • Misunderstanding the role of the Vector Address (it points to where the ISR is located).

Advanced Concepts

  • Vectored vs. Polled Interrupts
  • Interrupt Acknowledge (INTA) Cycles
  • Programmable Interrupt Controller (e.g., 8259A)
  • Edge-triggered vs. Level-triggered interrupts
  • Soft Priority (Dynamic Priority adjustment)

Practice Exercises

  • If devices A, B, and C request interrupts simultaneously in a daisy chain where A is closest to CPU, which gets served first?
  • How does a Priority Encoder resolve a situation where multiple inputs are active?
  • Explain the purpose of the 'Enable' bit in a parallel interrupt register.
  • Research why modern multi-core systems use APIC (Advanced Programmable Interrupt Controller).

Conclusion

Priority interrupt systems are crucial for managing the real-time demands of peripheral devices. While serial daisy chaining is cost-effective for simple systems, high-speed parallel encoders are necessary for modern, complex architectures to ensure fast and reliable interrupt handling.

Note: Note: In most modern PCs, the Interrupt Controller is integrated into the chipset (Southbridge) to manage dozens of system interrupts efficiently.