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Pipelining in Computer Architecture
Pipelining is a technique where multiple instructions are overlapped during execution. It is similar to an assembly line in a factory, where different stages of the process happen simultaneously on different units.
The 5 Stages of a RISC Pipeline
A standard processor breaks down an instruction into five distinct steps to allow for overlapping:
- **Instruction Fetch (IF):** Get the instruction from memory.
- **Instruction Decode (ID):** Read registers and translate the instruction.
- **Execute (EX):** Perform the actual operation (usually via the ALU).
- **Memory Access (MEM):** Read or write data to/from RAM if necessary.
- **Write Back (WB):** Write the result back into the register file.
Pipeline Hazards
Hazards are situations that prevent the next instruction in the instruction stream from executing in its designated clock cycle. They reduce the ideal speedup of the pipeline.
| Hazard Type | Cause | Solution |
|---|---|---|
| Structural Hazard | Hardware resource conflict (e.g., two instructions needing memory at once) | Increase hardware resources or separate memories |
| Data Hazard | Instruction depends on the result of a previous instruction still in the pipeline | Forwarding (Bypassing) or Stalling (Bubbles) |
| Control Hazard | Delay in determining the next instruction (caused by branches/jumps) | Branch prediction or Delayed branching |
Example Scenario: Data Forwarding
Without forwarding, the second instruction below must wait for the first to finish writing to the register. With forwarding, the result is sent directly from the ALU to the next stage.
ADD R1, R2, R3 ; R1 = R2 + R3
SUB R4, R1, R5 ; R4 = R1 - R5 (Depends on R1)Performance Metrics
In an ideal pipeline with $k$ stages, the speedup over a non-pipelined processor is approximately $k$, assuming no stalls occur.
Advanced Pipeline Concepts
- Super-pipelining (increasing the number of stages)
- Superscalar execution (multiple pipelines in one CPU)
- Out-of-order execution (Dynamic scheduling)
- Scoreboarding and Tomasulo’s Algorithm
- Branch Prediction Buffers
Common Mistakes to Avoid
- Thinking pipelining reduces the time to execute a single instruction (it actually improves throughput, not latency).
- Ignoring the overhead of pipeline registers.
- Confusing data hazards with structural hazards.
- Underestimating the impact of branch mispredictions.
Practice Exercises
- Calculate the total cycles for 10 instructions in a 5-stage pipeline with no hazards.
- Identify data dependencies in a given block of assembly code.
- Explain how 'flushing' the pipeline works during a branch misprediction.
- Draw a space-time diagram for a pipeline with one stall.
Conclusion
Pipelining is a fundamental pillar of modern CPU performance. While it introduces complexities like hazards, the massive gain in instruction throughput makes it indispensable in architecture design.